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1 ltc1066-1 14-bit dc accurate clock-tunable, 8th order elliptic or linear phase lowpass filter u a o pp l ic at i ty p i ca l frequency (hz) 100 10k 100k 1m 1066-1 ta02 1k gain (db) 10 0 10 20 30 40 50 60 70 80 ?0 f c = 800hz f c = 80khz amplitude response clock-tunable, dc accurate, 800hz to 80khz elliptic lowpass filter 7.5v 1066-1 ta01 7.5v 7.5v 7.5v v out ; v os(out) = 2.5mv max v in 40khz f clk 4mhz 1 m f 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 15pf out a in a +in a v v + connect 1 filter out 50/100 clk v + out b +in b gnd filter in comp 2 connect 2 comp 1 v ltc1066-1 20k 30k short connection under ic and shielded by a ground plane bypass the power supplies with 0.1 m f disc ceramic s f ea t u re n dc gain linearity: 14 bits n maximum dc offset: 1.5mv n dc offset tempco: 7 m v/ c n device fully tested at f cutoff = 80khz n maximum cutoff frequency: 120khz (v s = 8v) n drives 1k w load with 0.02% thd or better n signal-to-noise ratio: 90db n input impedance: 500m w n selectable elliptic or linear phase response n operates from single 5v up to 8v power supplies d u escriptio the ltc1066-1 is an 8th order elliptic lowpass filter which simultaneously provides clock-tunability and dc accu- racy. the unique and proprietary architecture of the filter allows 14 bits of dc gain linearity and a maximum of 1.5mv dc offset. an external rc is required for dc accurate operation. with 7.5v supplies, a 20k resistor and a 1 m f capacitor, the cutoff frequency can be tuned from 800hz to 100khz. a clock-tunable 10hz to 100khz operation can also be achieved (see typical application section). the filter does not require any external active components such as input/output buffers. the input/output impedance is 500m w /0.1 w and the output of the filter can source or sink 40ma. when pin 8 is connected to v + , the clock-to- cutoff frequency ratio is 50:1 and the input signal is sampled twice per clock cycle to lower the risk of aliasing. for frequencies up to 0.75f cutoff , the passband ripple is 0.15db. the gain at f cutoff is C1db and the filters stopband attenuation is 80db at 2.3f cutoff . linear phase operation is also available with a clock-to-cutoff frequency ratio of 100:1 when pin 8 is connected to ground. the ltc1066-1 is available in an 18-pin sol package. u s a o pp l ic at i n instrumentation n data acquisition systems n anti-aliasing filters n smoothing filters n audio signal processing
2 ltc1066-1 e lectr ic al c c hara terist ics (see test circuit) v s = 7.5v, r l = 1k, t a = 25 c, f clk signal level is ttl or cmos (maximum clock rise or fall time 1 m s) unless otherwise specified. all ac gain measurements are referenced to passband gain. parameter conditions min typ max units passband gain (0.01f cutoff to 0.25f cutoff )f clk = 400khz, f test = 2khz l C 0.18 0.16 0.36 db passband ripple (0.01f cutoff to 0.75f cutoff )f cutoff 50khz (see note on test circuit) 0.15 db for f clk /f cutoff = 50:1 gain at 0.50f cutoff for f clk /f cutoff = 50:1 f clk = 400khz, f test = 4khz C 0.09 0.02 0.09 db l C 0.14 0.05 0.14 db f clk = 2mhz, f test = 20khz C 0.16 C 0.05 0.02 db l C 0.22 C 0.10 0.02 db gain at 0.75f cutoff for f clk /f cutoff = 50:1 f clk = 400khz, f test = 6khz C 0.18 C 0.05 0.05 db l C 0.22 C 0.10 0.05 db f clk = 2mhz, f test = 30khz C 0.36 C 0.20 0.05 db l C 0.45 C 0.30 0.05 db f clk = 4mhz, f test = 60khz C 0.65 C 0.30 0.25 db l C 0.85 C 0.40 0.75 db gain at 1.00f cutoff for f clk /f cutoff = 50:1 f clk = 400khz, f test = 8khz C 1.50 C 1.10 C 0.05 db l C 1.80 C 1.20 C 0.05 db f clk = 2mhz, f test = 40khz C 2.10 C 1.60 C 1.20 db l C 2.30 C 1.60 C 1.20 db f clk = 4mhz, f test = 80khz C 2.20 C 1.60 C 0.05 db l C 2.50 C 1.60 0.25 db gain at 2.00f cutoff for f clk /f cutoff = 50:1 f clk = 400khz, f test = 16khz C 56 C 58 C 64 db l C54 C57 C64 db f clk = 2mhz, f test = 80khz C 53 C 56 C 62 db l C51 C55 C62 db f clk = 4mhz, f test = 160khz C 50 C 52 C 60 db l C48 C51 C60 db total supply voltage (v + to v C ) .......................... 16.5v power dissipation ............................................. 700mw burn-in voltage ................................................... 16.5v voltage at any input ..... (v C C 0.3v) v in (v + + 0.3v) maximum clock frequency v s = 8v ....................................................... 6.1mhz v s = 7.5v .................................................... 5.4mhz v s = 5v ....................................................... 4.1mhz v s = single 5v ............................................... 1.8mhz operating temperature range* .................. 0 c to 70 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number LTC1066-1CS t jmax = 110 c, q ja = 75 c/w top view s package 18-lead plastic sol 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 out a in a +in a v v + connect 1 filter out 50/100 clk v + out b +in b gnd filter in comp 2 connect 2 comp 1 v consult factory for other package options and for industrial and military grade parts. a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio * for an extended operating temperature range contact ltc marketing for details.
3 ltc1066-1 v s = 7.5v, r l = 1k, t a = 25 c, f clk signal level is ttl or cmos (maximum clock rise or fall time 1 m s) unless otherwise specified. all ac gain measurements are referenced to passband gain. parameter conditions min typ max units gain at f cutoff for f clk = 20khz, v s = 7.5v f clk /f cutoff = 50:1, f test = 400hz l C 1.75 C 1.25 C 0.50 db gain at f cutoff for v s = 2.375v, f clk /f cutoff = 50:1 f clk = 1mhz, f test = 20khz l C 1.75 C 0.70 0.10 db gain at 70khz for v s = 5v, f clk /f cutoff = 50:1 f clk = 4mhz, f test = 70khz l 1.00 1.40 db linear phase response phase at 0.25f cutoff f clk = 400khz, f test = 1khz C 48.5 C 50.0 C 51.5 deg f clk /f cutoff = 100:1, l C 48.0 C 50.0 C 52.0 deg pin 8 at gnd gain at 0.25f cutoff f clk = 400khz, f test = 1khz l C 0.65 C 0.25 0.25 db phase at 0.50f cutoff f clk = 400khz, f test = 2khz C 97.5 C 99.5 C 101.5 deg l C 97.0 C 99.5 C 102.0 deg gain at 0.50f cutoff f clk = 400khz, f test = 2khz l C 0.75 C 0.50 C 0.10 db phase at 0.75f cutoff f clk = 400khz, f test = 3khz C 148.0 C 150.5 C 152.5 deg l C 147.5 C 150.5 C 153.0 deg gain at 0.75f cutoff f clk = 400khz, f test = 3khz l C 1.40 C 1.00 C 0.60 db phase at f cutoff f clk = 400khz, f test = 4khz C 208.0 C 210.0 C 212.5 deg l C 207.5 C 210.0 C 213.0 deg gain at f cutoff f clk = 400khz, f test = 4khz l C 2.10 C 1.80 C 1.60 db input bias current v s = 2.375v 60 na l 70 135 na input offset current v s = 2.375v l 10 40 na v s 3 5v (note 2) l 10 45 na input offset current tempco 2.375v v s 7.5v 40 pa/ c output voltage offset tempco 2.375v v s 7.5v 7 m v/ c output offset voltage v s = 2.375v, f clk = 400khz 0.5 mv l 1.0 1.5 mv v s 3 5v 0.5 mv (note 2) l 1.0 1.5 mv common-mode rejection v s = 7.5v 90 96 db v cm = C 5v to 5v l 84 90 db power supply rejection v s = 2.5v to 7.5v 80 84 db l 78 82 db input voltage range and output voltage swing v s = 2.375v, r l = 1k 1.2 1.4 v l 1.1 v v s = 5v, r l = 1k 3.4 3.6 v l 3.2 v v s = 7.5v, r l = 1k 5.4 5.8 v l 5.0 v output short-circuit current 2.375v v s 7.5v 40 ma power supply current (note 1) v s = 2.375v 14 16 ma l 16 19 ma v s = 5v 22 26 ma l 23 29 ma v s = 7.5v 25 30 ma l 26 33 ma power supply range 2.375 8v e lectr ic al c c hara terist ics (see test circuit) the l denotes specifications which apply over the full operating temperature range. note 1: the maximum current over temperature is at 0 c. at 70 c the maximum current is less than its maximum value at 25 c. note 2: guaranteed by design and test correlation.
4 ltc1066-1 cc hara terist ics uw a t y p i ca lper f o r c e frequency (hz) 1k ?0 gain (db) ?0 ?0 ?0 ?0 10k 100k 1m 1066-1 g01 ?0 ?0 ?0 0 ?0 10 ?00 ?10 f clk = 500khz f clk = 5mhz v s = 7.5v t a = 25? f clk /f c = 50:1 compensation = 30k, 15pf f clk = 2.5mhz gain vs frequency v s = 7.5v, f clk /f c = 50:1 frequency (hz) 1k ?0 gain (db) ?0 ?0 ?0 ?0 10k 100k 1m 1066-1 g03 ?0 ?0 ?0 0 ?0 10 ?00 ?10 f clk = 1mhz f clk = 5mhz v s = 7.5v t a = 25? f clk /f c = 100:1 pin 8 to v frequency (hz) 1k ?0 gain (db) ?0 ?0 ?0 ?0 10k 100k 1m 1066-1 g02 ?0 ?0 ?0 0 ?0 10 ?00 ?10 f clk = 1mhz f clk = 5mhz v s = 7.5v t a = 25? f clk /f c = 100:1 no compensation pin 8 to agnd gain vs frequency v s = 7.5v, f clk /f c = 100:1 gain vs frequency v s = 7.5v, f clk /f c = 100:1 frequency (khz) 4 gain (db) ? 0 20 10666-1 g05 ? ? 6 12 16 phase (deg) 2 3 2 1 ? ? ? 180 120 60 0 60 120 ?80 240 300 360 810141822 linear phase response f c = 20khz, f clk /f c = 100:1 pin 8 at gnd, r f = 20k, c f = 1 m f (see block diagram) phase gain v s = 7.5v t a = 25? frequency (khz) 4 gain (db) ? 0 20 10666-1 g04 ? ? 6 12 16 phase (deg) 2 3 2 1 ? ? ? 180 120 60 0 60 120 ?80 240 300 360 810141822 elliptic response f c = 20khz, f clk = 1mhz f clk /f c = 50:1, pin 8 at v + r f = 20k, c f = 1 m f (see block diagram) phase gain v s = 7.5v t a = 25? frequency (khz) 4 gain (db) ? 0 20 10666-1 g06 ? ? 6 12 16 phase (deg) 2 3 2 1 ? ? ? 180 120 60 0 60 120 ?80 240 300 360 810141822 elliptic response f c = 20khz, f clk /f c = 100:1 pin 8 at v , r f = 20k, c f = 1 m f (see block diagram) phase gain v s = 7.5v t a = 25? frequency (khz) 1 ? gain (db) ? ? 1 3 10 100 1066-1 g08 ? ? 0 2 4 a d v s = 5v, t a = 70? f clk /f c = 50:1 r f = 20k, c f = 1 m f rc compensation =15pf in series with 30k w 5 b a. f clk = 1mhz b. f clk = 2mhz c. f clk = 3mhz d. f clk = 4mhz c frequency (khz) 1 gain (db) 10 50 1066-1 g07 3 2 1 0 1 ? ? ? ? ? v s = single 5v t a = 70? f clk /f c = 50:1 r f = 20k, c f = 1 m f rc compensation = 15pf in series with 30k w a. f clk = 1mhz (gnd = 2.5v) b. f clk = 1.4mhz (gnd = 2v) c. f clk = 1.8mhz (gnd = 2v) a b c passband gain and phase vs frequency passband gain and phase vs frequency passband gain and phase vs frequency passband gain vs frequency and f clk passband gain vs frequency and f clk
5 ltc1066-1 cc hara terist ics uw a t y p i ca lper f o r c e frequency (khz) 1 gain (db) 5 4 3 2 1 0 ? ? ? ? ? 10 100 1066-1 g09 200 a d v s = 7.5v, t a = 70? f clk /f c = 50:1 r f = 20k, c f = 1 m f rc compensation = 15pf in series with 30k w b a. f clk = 2mhz b. f clk = 3mhz c. f clk = 4mhz d. f clk = 5mhz c passband gain vs frequency group delay vs frequency frequency (khz) 2 20 group delay ( m s) 30 40 50 60 70 80 6101418 1066-1 g10 22 v s = 5v t a = 25? f c = 20khz 412 81620 a b c a. f clk /f c = 50:1 (pin 8 to v + ) b. f clk /f c = 100:1 (pin 8 to v ) c. linear phase reponse f clk /f c = 100:1 (pin 8 to gnd) frequency (f cutoff /frequency) 0.2 phase difference (deg) 1.25 1.00 0.75 0.50 0.25 0 0.8 a b 1066-1 g11 0.4 0.6 1.0 phase difference between any two units (sample of 50 representative units) v s 3 5v, t a = 25? f clk 2.5mhz a. elliptic response f clk /f c = 50:1 (pin 8 to v + ) b. linear phase response f clk /f c = 100:1 (pin8 to gnd) phase matching vs frequency thd + noise vs input voltage input voltage (v rms ) 0.1 1 5 1066-1 g12 ?0 ?0 ?0 ?0 ?5 ?5 ?0 ?5 ?0 ?5 ?5 t a = 25? f in = 1khz f clk = 1mhz f clk /f c = 50:1 v in thd + noise () (db) 20 log v s = 5v v s = ?.5v thd + noise vs input voltage input voltage (v rms ) 0.1 ?0 ?0 ?0 ?0 ?0 1 1066-1 g13 ?5 ?5 ?5 ?5 ?5 f in = 1khz v s = single 5v f clk = 1mhz f clk /f c = 50:1 t a = 25? ?0 2 v in thd + noise () (db) 20 log gnd pin 15 at 2v gnd pin 15 at 2.5v thd + noise vs frequency frequency (khz) 11050 1066-1 g14 ?0 ?0 ?0 ?0 ?5 ?5 ?0 ?5 ?0 ?5 ?5 v s = 7.5v v in = 1v rms t a = 25? f clk = 2.5mhz f clk /f c = 50:1 (5 representative units) v in thd + noise () (db) 20 log frequency (khz) 11050 1066-1 g15 ?0 ?0 ?0 ?0 ?5 ?5 ?0 ?5 ?0 ?5 ?5 v s = ?.5v v in = 1v rms t a = 25? f clk = 2.5mhz f clk /f c = 50:1 a. r l = , c l = 100pf b. r l = 1k, c l = 100pf c. r l = 200 w , c l = 100pf a b c v in thd + noise () (db) 20 log thd + noise vs frequency thd + noise vs frequency thd + noise vs frequency frequency (khz) 1 ?0 ?0 ?0 ?0 ?0 10 1066-1 g16 ?5 ?5 ?5 ?5 ?5 v s = 5v v in = 1v rms t a = 25? f clk = 1mhz f clk /f c = 50:1 (5 representative units) ?0 20 v in thd + noise () (db) 20 log frequency (khz) 1 ?0 ?0 ?0 ?0 ?0 10 1066-1 g17 ?5 ?5 ?5 ?5 ?5 v s = single 5v v in = 0.5v rms t a = 25? f clk = 1mhz f clk /f c = 50:1 (5 representative units) ?0 20 v in thd + noise () (db) 20 log
6 ltc1066-1 cc hara terist ics uw a t y p i ca lper f o r c e total power supply voltage (v) 0 2 6 10 14 18 power supply current (ma) 30 27 24 21 18 15 12 9 6 3 0 16 1066-1 g18 4 8 12 20 0? 25? 70? power supply current vs power supply voltage 100 m s/div linear phase (pin 8 to gnd) f in = 1khz, f cutoff = 10khz 1066-1 g20 transient response 1v/div 1v/div 100 m s/div elliptic response (pin 8 to v + ) f in = 1khz, f cutoff = 10khz 1066-1 g19 transient response table 1. elliptic response, f c = 10khz, f clk /f cutoff = 50:1, v s = 7.5v, r f = 20k, c f = 1 m f, no rc compensation, t a = 25 c frequency gain phase group delay (khz) (db) (deg) ( m s) 2.000 0.117 C 50.09 70.52 3.000 0.118 C 75.75 72.04 4.000 0.116 C 101.96 74.32 5.000 0.112 C 129.25 77.59 6.000 0.104 C 157.82 82.04 7.000 0.074 171.68 88.56 8.000 C 0.014 138.41 97.80 9.000 C 0.278 101.26 110.33 10.000 C 0.986 58.98 124.91 table 2. elliptic response, f c = 50khz, f clk /f cutoff = 50:1, v s = 7.5v, r f = 20k, c f = 1 m f, no rc compensation, t a = 25 c frequency gain phase group delay (khz) (db) (deg) ( m s) 10.000 0.104 C 50.91 14.32 15.000 0.105 C 76.95 14.61 20.000 0.107 C 103.51 15.05 25.000 0.109 C 131.13 15.70 30.000 0.107 C 160.03 16.57 35.000 0.089 169.22 17.85 40.000 0.014 135.72 19.66 45.000 C 0.231 98.44 22.10 50.000 C 0.905 56.15 24.93 table 3. linear phase response, f c = 10khz, f clk /f cutoff = 100:1, v s = 7.5v, r f = 20k, c f = 1 m f, no rc compensation, t a = 25 c frequency gain phase group delay (khz) (db) (deg) ( m s) 2.000 C 0.020 C 39.96 55.25 3.000 C 0.181 C 59.76 55.03 4.000 C 0.383 C 79.60 54.98 5.000 C 0.601 C 99.34 55.28 6.000 C 0.811 C 119.40 56.34 7.000 C 1.004 C 139.91 58.56 8.000 C 1.196 C 161.56 62.34 9.000 C 1.451 175.21 67.29 10.000 C 1.910 149.99 72.31 table 4. linear phase response, f c = 50khz, f clk /f cutoff = 100:1, v s = 7.5v, r f = 20k, c f = 1 m f, no rc compensation, t a = 25 c frequency gain phase group delay (khz) (db) (deg) ( m s) 10.000 0.039 C 40.72 11.30 15.000 C 0.068 C 61.01 11.31 20.000 C 0.202 C 81.42 11.36 25.000 C 0.345 C 101.88 11.48 30.000 C 0.479 C 122.74 11.73 35.000 C 0.594 C 144.09 12.20 40.000 C 0.701 C 166.68 12.99 45.000 C 0.860 169.15 14.06 50.000 C 1.214 142.72 15.19
7 ltc1066-1 level threshold values for a dual or single supply operation. sine waves are not recommended for clock input frequen- cies less than 100khz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time 1 m s). the clock signal should be routed from the left side of the ic package and perpendicular to it to avoid coupling to any input or output analog signal path. a 200 w resistor between clock source and pin 9 will slow down the rise and fall times of the clock to further reduce charge coupling. table 5. clock source high and low threshold levels power supply high level low level dual supply = 7.5v 3 2.18v 0.5v dual supply = 5v 3 1.45v 0.5v dual supply = 2.5v 3 0.73v C 2.0v single supply = 12v 3 7.80v 6.5v single supply = 5v 3 1.45v 0.5v 50:1/100:1 pin (8) the dc level at pin 8 determines the ratio of the clock to the filter cutoff frequency. when pin 8 is connected to v + the clock-to-cutoff frequency ratio (f clk /f cutoff ) is 50:1 and the filter response is elliptic. the design of the internal switched-capacitor filter was optimized for a 50:1 operation. when pin 8 is connected to ground (or 1/2 supply for single supply operation), the f clk /f cutoff ratio is equal to 100:1 and the filter response is pseudolinear phase (see group delay vs frequency in typical performance charac- teristic section). when pin 8 is connected to v C (or ground for single supply operation), the f clk /f cutoff ratio is 100:1 and the filter response is transitional butterworth elliptic. the typical performance characteristics provide all the necessary information. if the dc level at pin 8 is mechanically switched, a 10k resistor should be connected between pin 8 and the dc source. input pins (2, 3, 14, 16) pin 3 (+in a) and pin 2 (Cin a) are the positive and negative inputs of an internal high performance op amp a pi n fu n ctio n s uuu power supply pins (5, 18, 4, 10) the power supply pins should be bypassed with a 0.1 m f capacitor to an adequate analog ground. the bypass capacitors should be connected as close as possible to the power supply pins. the v + pins (5, 18) and the v C pins (4, 10) should always be tied to the same positive supply and negative supply value respectively. low noise linear sup- plies are recommended. switching power supplies are not recommended as they will lower the filter dynamic range. when the ltc1066-1 is powered up with dual supplies and, if v + is applied prior to a floating v C , connect a signal diode (1n4148) between pin 10 and ground to prevent power supply reversal and latch-up. a signal diode (1n4148) is also recommended between pin 5 and ground if the negative supply is applied prior to the positive supply and the positive supply is floating. note, in most labora- tory supplies, reversed biased diodes are always con- nected between the supply output terminals and ground, and the above precautions are not necessary. however, when the filter is powered up with conventional 3-terminal regulators, the diodes are recommended. analog ground pin (15) the filter performance depends on the quality of the analog signal ground. for either dual or single supply operation, an analog ground plane surrounding the pack- age is recommended. the analog ground plane should be connected to any digital ground at a single point. for dual supply operation, pin 15 should be connected to the analog ground plane. for single supply operation pin 15 should be biased at 1/2 supply and should be bypassed to the analog ground plane with at least a 1 m f capacitor (see typical applications). for single 5v operation and for f clk 3 1.4mhz, pin 15 should be biased at 2v. this minimizes passband gain and phase variations. clock input pin (9) any ttl or cmos clock source with a square-wave output and 50% duty cycle ( 10%) is an adequate clock source for the device. the power supply for the clock source should not be the filters power supply. the analog ground for the filter should be connected to clocks ground at a single point only. table 5 shows the clocks low and high
8 ltc1066-1 15pf capacitor should be connected between pins 11 and 13. compensation is recommended for the following cases shown in table 6. table 6. cases where an rc compensation (15pf in series with 30k w pins 11, 13) is recommended, f clk /f cutoff = 50:1 v s = single 5v (agnd = 2v) t a = 25 cf cutoff 3 28khz t a = 70 cf cutoff 3 24khz v s = 5v t a = 25 cf cutoff 3 60khz t a = 70 cf cutoff 3 50khz v s = 7.5v t a = 25 cf cutoff 3 70khz t a = 70 cf cutoff 3 60khz connect pins (6, 12) pin 6 (connect 1) and pin 12 (connect 2) should be shorted. in a printed circuit board the connection should be done under the ic package through a short trace surrounded by the analog ground plane. pin 6 should be 0.2 inches away from any other circuit trace. pi n fu n ctio n s uuu (see block diagram). input bias current flows out of pins 2 and 3. pin 16 (+in b) is the positive input of a high performance op amp b which is internally connected as a unity-gain follower. op amp b buffers the switched- capacitor network output. the input capacitance of both op amps is 10pf. pin 14 (filter in ) is the input of a switched-capacitor network. the input impedance of pin 14 is typically 11k. output pins (1, 7, 17) pins 1 and 17 are the outputs of the internal high perfor- mance op amps a and b. pin 1 is usually connected to the internal switched-capacitor filter network input pin 14. pin 17 is the buffered output of the filter and it can drive loads as heavy as 200 w (see thd + noise curves under typical performance characteristics). pin 7 is the internal switched- capacitor network output and it can typically sink or source 1ma. compensation pins (11, 13) pins 11 and 13 are the ac compensation pins. if compen- sation is needed, an external 30k resistor in series with a block diagra m w filter in connect 1 comp1 comp2 connect 2 filter out 8th order switched- capacitor network 5,18 4,10 15 8 9 6 7 16 17 12 13 11 14 1 3 2 in a +in a v + v gnd 50/100 clk +in b patent pending ltc1066-1 out b out a c f r f 11066-1 bd + high speed op amp + high speed op amp
9 ltc1066-1 test circuit 1066-1 tc01 note: rc compensation between pins 11 and 13 is required only for clock-tunable operation for: 50khz < f cutoffs 100khz. the test specifications for: f clk = 2mhz, f cutoff = 40khz, and f clk = 4mhz, f cutoff = 80khz include the effects of rc compensation. compensation does not influece the specifications for: f clk = 400khz, f cutoff = 8khz. for clock-tunable f cutoffs from 2khz to 50khz compensation is not required and the filter? passband performance is represented by the typical specifications at: f clk = 400khz, f cutoff = 8khz. v + v + v v v + v out v in f clk (duty cycle = 50% ?0% ) elliptic response 50:1 linear phase response 100:1 1 m f 0.1 m f 15pf 0.1 m f 0.1 m f 10k 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 20k 20 w 30k ltc1066-1 0.1 m f 20 w out a in a +in a v v + connect 1 filter out 50/100 clk v + out b +in b gnd filter in comp 2 connect 2 comp 1 v applicatio n s i n for m atio n wu u u dc performance the dc performance of the ltc1066-1 is dictated by the dc characteristics of the input precision op amp. 1. dc input voltages in the vicinity of the filters half of the total power supply are processed with exactly 0db (or 1v/ v) of gain. 2. the typical dc input voltage ranges are equal to: v in = 5.8v, v s = 7.5v v in = 3.6v, v s = 5v v in = 1.4v, v s = 2.5v with an input dc voltage range of v in = 5v, (v s = 7.5v), the measured cmrr was 100db. figure 1 shows the dc gain linearity of the filter exceeding the requirements of a 14-bit, 10v full scale system. 3. the filter output dc offset v os(out) is measured with the input grounded and with dual power supplies. the v os(out) is typically 0.1mv and it is optimized for the filter connection shown in the test circuit figure. the filter output offset is equal to: v os(out) = v os (op amp a) Ci bias r f = 0.1mv (typ) 4. the v os(out) temperature drift is typically 7 m v/ c (t a > 25 c), and C 7 m v/ c (t a < 25 c). 5. the v os(out) temperature drift can be improved by using an input resistor r in equal to the feedback resis- input voltage (vdc) ? ? ? ? 1 3 5 v in ?v out ( m v) 75 50 25 0 25 50 75 100 125 2 1066-1 f01 ? ? 0 46 v s = 7.5v t a = 25? f clk = 1mhz f c = 20khz figure 1. dc gain linearity tor r f , however, the absolute value of v os(out) will increase. for instance, if a 20k resistor is added in series with pin 3 (see test circuit), the output v os drift will be improved by 2 m v/ c to 3 m v/ c, however, the v os(out) may increase by 1mv (max) . 6. the filter dc output offset voltage v os(out) is indepen- dent from the filter clock frequency (f clk 250khz). figures 2 and 3 show the v os(out) variation for three different power supplies and for clock frequencies up to 5mhz. both figures were traced with the ltc1066-1 soldered into the pc board. power supply decoupling is very important, especially with 7.5v supplies. if nec- essary connect a small resistor (20 w ) between pins 5
10 ltc1066-1 applicatio n s i n for m atio n wu u u absolutely perfect 0db dc gain and phases into an imper- fect ac passband gain, typically 0.1db. the filters low passband ripple, typically 0.05db, is mea- sured with respect to the ac passband gain. the ltc1066-1 dc stabilizing loop slightly warps the filters passband performance if the C 3db frequency of the feedback passive elements (1/2 p r f c f ) is more than the cutoff frequency of the internal switched-capacitor filter divided by 250. the ltc1066-1 clock tunability directly relates to the above constraint. figure 4 illustrates the passband behavior of the ltc1066-1 and it demonstrates the clock tunability of the device. a typical ltc1066-1 device was used to trace all four curves of figure 4. curve d, for instance, has nearly zero ripple and 0.04db pass- band gain. curve ds 20khz cutoff is much higher than the 8hz cutoff frequency of the r f c f feedback network, so its passband is free from any additional error due to r f c f feedback elements. curve b illustrates the passband error when the 1mhz clock of curve d is lowered to 100khz. a 0.1db error is added to the filters original ac gain of 0.04db. ac performance ac (passband) gain the passband gain of the ltc1066-1 is equal to the passband gain of the internal switched-capacitor lowpass filter, and it is measured at f = 0.25f cutoff . unlike conven- tional monolithic filters, the ltc1066-1 starts with an frequency (hz) 10 gain (db) 100 1k 10k 20k 1066-1 f04 1.00 0.75 0.50 0.25 0 0.25 0.50 0.75 1.00 t a = 25? f clk /f c = 50:1 r f = 20k, c f = 1 m f curve d: f cutoff = 20khz = 2500 2 p r f c f 1 curve c: f cutoff = 5khz = 625 2 p r f c f 1 curve b: f cutoff = 2khz = 250 2 p r f c f 1 curve a: f cutoff = 1khz = 125 2 p r f c f 1 a b cd and 18, and between pins 10 and 4, to isolate the precision op amp supply pin from the switched-capaci- tor network supply (see the test circuit). clock frequency (mhz) 0 0.5 1.5 2.5 3.5 4.5 filter output offset voltage change (mv) 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 4.0 1066-1 f02 1.0 2.0 3.0 5.0 v s = 2.5v v s = 5v v s = 7.5v linear phase t a = 25? f clk /f c = 100:1 clock frequency (mhz) 0 0.5 1.5 2.5 3.5 4.5 filter output offset voltage change (mv) 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 4.0 1066-1 f03 1.0 2.0 3.0 5.0 v s = 2.5v v s = 5v v s = 7.5v t a = 25? f clk /f c = 50:1 figure 2. output offset change vs clock (relative to offset for f clk = 250khz) figure 3. output offset change vs clock (relative to offset for f clk = 250khz) figure 4. passband behavior
11 ltc1066-1 applicatio n s i n for m atio n wu u u transient response and settling time the ltc1066-1 exhibits two different transient behaviors. first, during power-up the dc correcting loop will settle after the voltage offset of the internal switched-capacitor network is stored across the feedback capacitor c f (see block diagram). it takes approximately five time constants (5r f c f ) for settling to 1%. second, following dc loop settling, the filter reaches steady state. the filter transient response is then defined by the frequency characteristics of the internal switched-capacitor lowpass filter. figure 5 shows details. dc loop settling is also observed if, at steady state, the dc offset of the internal switched-capacitor network suddenly changes. a sudden change may occur if the clock fre- quency is instantaneously stepped to a value above 1mhz. input 90% 50% 10% output t r t d t s 1066-1 f05 rise time (t r ) settling time (t s ) delay time (t d ) 50:1 elliptic 0.43 f cutoff 3.4 f cutoff 0.709 f cutoff 5% 5% 5% 0.43 f cutoff 2.05 f cutoff 0.556 f cutoff 5% 5% 5% 100:1 linear phase and on the value of the power supplies. with proper layout techniques the values of the clock feedthrough are shown on table 7. table 7. clock feedthrough power supply 50:1 100:1 single 5v 70 m v rms 90 m v rms 5v 100 m v rms 200 m v rms 7.5v 160 m v rms 650 m v rms wideband noise the wideband noise of the filter is the total rms value of the devices noise spectral density and is used to deter- mine the operating signal-to-noise ratio. most of its fre- quency contents lie within the filter passband and cannot be reduced with post filtering. for instance, the ltc1066- 1 wideband noise at 5v supply is 100 m v rms , 95 m v rms of which have frequency contents from dc up to the filters cutoff frequency. the total wideband noise ( m v rms ) is nearly independent of the value of the clock. the clock feedthrough specifications are not part of the wideband noise. table 8 lists the typical wideband noise for each supply. table 8. wideband noise power supply 50:1 100:1 (pin 8 to gnd) single 5v 90 m v rms 80 m v rms 5v 100 m v rms 85 m v rms 7.5v 106 m v rms 90 m v rms speed limitations to avoid op amp slew rate limiting at maximum clock frequencies, the signal amplitude should be kept below a specified level as shown in table 9. table 9. maximum v in input frequency maximum v in 3 250khz 0.50v rms 3 700khz 0.25v rms clock feedthrough clock feedthrough is defined as the rms value of the clock frequency and its harmonics that are present at the filters output pin (9). the clock feedthrough is tested with the input pin (2) grounded and depends on pc board layout figure 5. transient response
12 ltc1066-1 applicatio n s i n for m atio n wu u u aliasing in a sampled-data system the sampling theorem says that if an input signal has any frequency components greater than one half the sampling frequency, aliasing errors will appear at the output. in practice, aliasing is not always a serious problem. high order switched-capacitor lowpass filters are inherently band limited and significant aliasing occurs only for input signals centered around the clock frequency and its multiples. figure 6 shows the ltc1066-1 aliasing response when operated with a clock-to-cutoff frequency ratio of 50:1. with a 50:1 ratio ltc1066-1 samples its input twice during one clock period and the sampling frequency is equal to two times the clock frequency. the figure also shows the maximum aliased output gener- ated for inputs in the range of 2f clk f c . for instance, if the ltc1066-1 is programmed to produce a cutoff frequency of 20khz with 1mhz clock, a 10mv, 1.02mhz input signal will cause a 10 m v aliased signal at 20khz. this signal will be buried in the noise. maximum aliasing will occur only for input signals in the narrow range of 2mhz 20khz or multiples of 2mhz. figure 7 shows the ltc1066-1 aliased response when operated with a clock-to-cutoff frequency ratio of 100:1 (linear phase response with pin 8 to ground). figure 6. aliasing vs frequency f clk /f c = 50:1 (pin 8 to v + ) clock is a 50% duty cycle square wave aliased output (db) 0 ?0 ?0 input frequency 1066-1 f06 f clk ?f c 2f clk ?f c 2f clk ?2.3f c 2f clk + 2.3f c f clk + f c 2f clk + f c f clk 2f clk aliased output (db) 0 ?6 ?5 input frequency 1066-1 f07 f clk ?f c 2f clk ?f c 2f clk ?4f c f clk ?4f c f clk + 4f c 2f clk + 4f c f clk + f c 2f clk + f c f clk 2f clk figure 7. aliasing vs frequency f clk /f c = 100:1 (pin 8 to ground) clock is a 50% duty cycle square wave
13 ltc1066-1 typical applicatio n s u dual supply operation dc accurate, 10hz to 100khz , clock-tunable, 8th order elliptic lowpass filter f clk /f c = 50:1 7.5v 1066-1 ta03 7.5v 7.5v 7.5v 7.5v v out v in f clk 33 m f 0.1 m f 1n4148* 1n4148* 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 0.1 m f 15pf out a in a +in a v v + connect 1 filter out 50/100 clk v + out b +in b gnd filter in comp 2 connect 2 comp 1 v 0.1 m f 0.1 m f 0.1 m f ltc1066-1 100k 200 w 30k 20 w 20 w 100k maximum output voltage offset = 5.5mv, dc linearity = 0.0063%, t a = 25?. the pins 6 to 12 connection should be under the ic and shielded by an analog system ground plane. rc compensation between pins 11 and 13 required only for f cutoff 3 60khz. the 33 m f capacitor is a nonpolarized, aluminum electrolytic, 20%, 16v (nichicon uupic 330mcrigs or nic nacen 33m16v 6.3 5.5 or equivalent). * protection diodes, 1n4148 are optional. see pin descriptions. single 5v supply operation dc accurate, 10hz to 36khz , clock-tunable, 8th order elliptic lowpass filter f clk /f c = 50:1 5v 1066-1 ta04 5v 5v v out v in f clk 33 m f 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 0.1 m f 15pf out a in a +in a v v + connect 1 filter out 50/100 clk v + out b +in b gnd filter in comp 2 connect 2 comp 1 v 0.1 m f 0.1 m f 1 m f ltc1066-1 100k 200 w 30k 100k 10k 10k input linear range = 1.4v to 3.6v. dc linearity = 0.0063%. the pins 6 to 12 connection should be under the ic and shielded by an analog system ground plane. rc compensation between pins 11 and 13 required only for f cutoff 3 24khz. the 33 m f capacitor is a nonpolarized, aluminum electrolytic, 20%, 16v (nichicon uupic 330mcrigs or nic nacen 33m16v 6.3 5.5)
14 ltc1066-1 typical applicatio n s u 1066-1 ta06 7.5v 7.5v 7.5v 2nd order rc anti-aliasing filter provides 36db attenuation to inputs at 2f clk ?.5v v out v in f clk 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 out a in a +in a v v + connect 1 filter out 50/100 clk v + out b +in b gnd filter in comp 2 connect 2 comp 1 v 0.1 m f 0.1 m f 0.1 m f ltc1066-1 20 w 20 w 402 w 1k 20k 0.1 m f 1 m f c c f 3db = 5f cutoff c = m f (f 3db in hz) f cutoff = f clk 50 100 f 3db f 3db is the ?db frequency of the 2nd order rc filter dc accurate lowpass filter with input anti-aliasing (f clk 250khz) dc accurate lowpass filter with input anti-aliasing (f clk > 250khz) 1066-1 ta05 7.5v 7.5v 7.5v 2nd order butterworth anti- aliasing filter provides 68db attenuation to inputs at 2f clk ?.5v v out v in f clk c f r f 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 c2 out a in a +in a v v + connect 1 filter out 50/100 clk v + out b +in b gnd filter in comp 2 connect 2 comp 1 v 0.1 m f 0.1 m f 0.1 m f ltc1066-1 20 w 20 w r1 r2 0.1 m f c1 f cutoff = , = f clk 50 f cutoff 250 1 2 p r f c f = 2hz, set r f = 80.6k, c f = 1 m f and c1 = 0.0027 m f 1 2 p r f c f f 3db = 2? cutoff (f 3db is the ?db frequency of the 2nd order anti-aliasing filter) 1 2 p( r1 + r2)c1 = 0.707f 3db , r2 = 17.946r1, c2 = 10c1 for cutoff frequencies 2khz to 5khz, set r f = 20k, c f = 1 m f and r1 + r2 2k for cutoff frequencies <2khz, set r1 + r2 = r f for example: if the cutoff frequency of ltc1066-1 is 500hz, then f 3db = 1000hz r1 + r2 = 80.6k, r1 = 4.22k and r2 = 76.8k rounded to nearest 1% value. c2 = 0.027 m f rounded to nearest standard value. note: r f should be 100k to minimize dc offset to 5.5mv
15 ltc1066-1 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. typical applicatio n s u dc accurate clock-tunable lowpass filter with tunable input anti-aliasing filter (circuit provides at least C 20db attenuation to input frequencies at 2f clk . the clock-tunable range is 5 octaves.) + + + + 13 12 11 10 r f + + + v in c p 50pf c a 0.047 m f 0.1 m f 7 9 5 12 5 7 8 10 9 15 16 2 6 11 14 3 1 4 3 2 8 15 16 17 18 413 19 ltc1045 14 r a pulse output 6 r p 2k 12.1k 1k 500 w 500 w 0.1 m f 0.1 m f clock input (ttl or cmos) pulse average clock frequency detector 20 ltc1045 1 1 m f 5v 0.1 m f 0.1 m f 0.1 m f ltc202 ?v 5v 5v c3 c2 r1 1k r in * 200 w 20 w 20 w clock-tunable, 8th order lowpass filter first order rc lowpass anti-aliasing filter 1 c f 18 0.1 m f c1 c in * 0.1 m f 0.1 m f 0.1 m f v out 0.1 m f 0.1 m f ?v c4 c5 217 316 415 514 613 712 811 910 v + out b +in b gnd ltc1066-1 f in comp 2 con 2 comp 1 v out a in a +in a v v + con 1 f out 50/100 clk component calculations for a clock-tunable range of five octaves: definitions: 1. the cutoff frequency of ltc1066-1 is abbreviated as f c 2. f c(low) is the lowest cutoff frequency of interest 3. a range of five octaves is from f c(low) to 32f c(low) component calculations: example: 1 2 p r f c f f c(low) 125 1 f c(low) = ; r in * = r f (if r f can be chosen to be 20k, r in and c in are omitted. f c(low) /125 allows for 0.2db gain peak in the passband) c1 = m f (f c(low) in hz) ; r1 = 1k 10 5 50? c(low) 5 10 5 50? c(low) c p = 50pf; r p = k c a = 0.047 m f; r a = k c2 = c1, c3 = 2c1, c4 = 4c1, c5 = 8c1 let? choose a five octave range from 1khz to 32khz. f c(low) = 1khz (1000hz). let c f = 1 m f, then r f calculates to be 20k. r in and c in omitted; r1 = 1k, c1 = 0.001 m f, c2 = 0.001 m f, c3 = 0.0022 m f, c4 = 0.0039 m f, c5 = 0.0082 m f. c p = 50pf, r p = 2k, c a = 0.047 m f, r a = 10k 1066-1 ta08
16 ltc1066-1 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 ? linear technology corporation 1994 lt/gp 0594 10k ? printed in usa typical applicatio n s u 100khz elliptic lowpass filter with input anti-aliasing and output clock feedthrough filters (not dc accurate) package descriptio n u dimensions in inches (millimeters) unless otherwise noted. see note 0.447 ?0.463 (11.354 ?11.760) (note 2) 15 14 13 12 11 10 16 9 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 17 18 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ 0??8?typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299 (7.391 ?7.595) (note 2) 45 0.010 ?0.029 (0.254 ?0.737) 0.005 (0.127) rad min note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options. 2. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.006 inch (0.15mm). s package 18-lead plastic sol frequency (hz) 10k gain (db) 100k 1m 10m 1066-1 ta07b 10 0 10 20 30 40 50 60 70 80 90 100 gain vs frequency 1066-1 ta07a 8v ?v output clock feedthrough filter 8v 2nd order butterworth input anti-aliasing filter provides 68db attenuation to inputs at 2f clk . f 3db = 200khz ?v v out v in f clk c1 51pf c2 510pf 20pf 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 out a in a +in a v v + connect 1 filter out 50/100 clk v + out b +in b gnd filter in comp 2 connect 2 comp 1 v 0.1 m f 0.1 m f 0.1 m f ltc1066-1 100 w 30k 2.49k 2.49k 10k 0.1 m f 1000pf f 3db = 2f cutoff f cutoff = c1 = c2 = m f (f 3db in hz) f clk 50 c2 10 100 f 3db

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